Design of memory subsystem for wide input data range in the SALT ASIC

The paper presents the design and optimisation of memory buffer in the SALT (Silicon ASIC for LHCb Tracking) ASIC. The SALT is a new 128-channel readout ASIC for silicon strip detectors in the Large Hadron Collider beauty (LHCb) experiment at the Large Hadron Collider (LHC) in CERN. The stochastic nature of phenomena detected by the ASIC results in a very different amount of data after each collision of particles. The SALT generates a data packet which size may vary between one and 100 bytes in each clock cycle and which should be stored in a memory buffer regardless of its size. The memory buffer is based on a number of macro blocks. The input size of the macro block is a free parameter of the design so the optimization was performed taking into account occupied area and consumed power. A full 128-channel version, designed in CMOS 130 nm technology, together with implemented memory buffer, was submitted, produced and is being tested. The tests show full functionality of the ASIC and memory buffer.