Results from CHIPIX-FE0, a small-scale prototype of a new generation pixel readout ASIC in 65 nm CMOS for HL-LHC

A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a m...

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Detalles Bibliográficos
Autores principales: Pacher, Luca, Monteil, Ennio, Paternò, Andrea, Panati, Serena, Demaria, Natale, Rivetti, Angelo, Da Rocha Rolo, Manuel Dionisio, Dellacasa, Giulio, Mazza, Giovanni, Rotondo, Francesco, Wheadon, Richard, Loddo, Flavio, Licciulli, Francesco, Ciciriello, Fabio, Marzocca, Cristoforo, Gaioni, Luigi, Traversi, Gianluca, Re, Valerio, De Canio, Francesco, Ratti, Lodovico, Marconi, Sara, Placidi, Pisana, Magazzù, Guido, Stabile, Alberto, Mattiazzo, Serena
Lenguaje:eng
Publicado: SISSA 2017
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.22323/1.313.0024
http://cds.cern.ch/record/2312585

Internet

https://dx.doi.org/10.22323/1.313.0024
http://cds.cern.ch/record/2312585

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