A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit with High Speed Feed Forward Correction in 65 nm CMOS

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A fault tolerant, radiation hardened Clock and Data Recovery (CDR) architecture is presented for high-energy physics and space applications. The CDR employs a novel soft-error tolerant Voltage Controlled Oscillator (VCO) and includes a high-speed feed-forward path to stabilize the CDR to compensate...

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Detalles Bibliográficos
Autores principales: Prinzie, Jeffrey, Kulis, Szymon, Leitao, Pedro, Francisco, Rui, Smedt, Valentijn De, Moreira, Paulo, Leroux, Paul
Lenguaje:eng
Publicado: 2019
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1109/LASCAS.2019.8667542
http://cds.cern.ch/record/2701582

Internet

https://dx.doi.org/10.1109/LASCAS.2019.8667542
http://cds.cern.ch/record/2701582

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