A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit with High Speed Feed Forward Correction in 65 nm CMOS

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A fault tolerant, radiation hardened Clock and Data Recovery (CDR) architecture is presented for high-energy physics and space applications. The CDR employs a novel soft-error tolerant Voltage Controlled Oscillator (VCO) and includes a high-speed feed-forward path to stabilize the CDR to compensate...

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Autores principales: Prinzie, Jeffrey, Kulis, Szymon, Leitao, Pedro, Francisco, Rui, Smedt, Valentijn De, Moreira, Paulo, Leroux, Paul
Lenguaje:eng
Publicado: 2019
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1109/LASCAS.2019.8667542
http://cds.cern.ch/record/2701582
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author Prinzie, Jeffrey
Kulis, Szymon
Leitao, Pedro
Francisco, Rui
Smedt, Valentijn De
Moreira, Paulo
Leroux, Paul
author_facet Prinzie, Jeffrey
Kulis, Szymon
Leitao, Pedro
Francisco, Rui
Smedt, Valentijn De
Moreira, Paulo
Leroux, Paul
author_sort Prinzie, Jeffrey
collection CERN
description A fault tolerant, radiation hardened Clock and Data Recovery (CDR) architecture is presented for high-energy physics and space applications. The CDR employs a novel soft-error tolerant Voltage Controlled Oscillator (VCO) and includes a high-speed feed-forward path to stabilize the CDR to compensate for an additional pole in the VCO to harden it against ionizing particles. The CDR has a data rate of 2.56 Gbps and uses In-Phase/Quadrature (IQ) clocks in combination with a frequency detector (FD) to increase the pull-in range. The circuit was designed in a 65 nm CMOS technology and has a core power consumption of only 34 mW.
id oai-inspirehep.net-1741335
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2019
record_format invenio
spelling oai-inspirehep.net-17413352020-01-10T09:53:11Zdoi:10.1109/LASCAS.2019.8667542http://cds.cern.ch/record/2701582engPrinzie, JeffreyKulis, SzymonLeitao, PedroFrancisco, RuiSmedt, Valentijn DeMoreira, PauloLeroux, PaulA Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit with High Speed Feed Forward Correction in 65 nm CMOSDetectors and Experimental TechniquesA fault tolerant, radiation hardened Clock and Data Recovery (CDR) architecture is presented for high-energy physics and space applications. The CDR employs a novel soft-error tolerant Voltage Controlled Oscillator (VCO) and includes a high-speed feed-forward path to stabilize the CDR to compensate for an additional pole in the VCO to harden it against ionizing particles. The CDR has a data rate of 2.56 Gbps and uses In-Phase/Quadrature (IQ) clocks in combination with a frequency detector (FD) to increase the pull-in range. The circuit was designed in a 65 nm CMOS technology and has a core power consumption of only 34 mW.oai:inspirehep.net:17413352019
spellingShingle Detectors and Experimental Techniques
Prinzie, Jeffrey
Kulis, Szymon
Leitao, Pedro
Francisco, Rui
Smedt, Valentijn De
Moreira, Paulo
Leroux, Paul
A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit with High Speed Feed Forward Correction in 65 nm CMOS
title A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit with High Speed Feed Forward Correction in 65 nm CMOS
title_full A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit with High Speed Feed Forward Correction in 65 nm CMOS
title_fullStr A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit with High Speed Feed Forward Correction in 65 nm CMOS
title_full_unstemmed A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit with High Speed Feed Forward Correction in 65 nm CMOS
title_short A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit with High Speed Feed Forward Correction in 65 nm CMOS
title_sort low noise fault tolerant radiation hardened 2.56 gbps clock-data recovery circuit with high speed feed forward correction in 65 nm cmos
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1109/LASCAS.2019.8667542
http://cds.cern.ch/record/2701582
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