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A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit With High Speed Feed Forward Correction in 65 nm CMOS
A fault tolerant, radiation hardened Clock and Data Recovery (CDR) architecture is presented for high-energy physics and space applications. The CDR employs a novel soft-error tolerant Voltage Controlled Oscillator (VCO) and includes a high-speed feed-forward path, which stabilizes the CDR by compen...
| Autores principales: | , , , , , , |
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| Lenguaje: | eng |
| Publicado: |
2019
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| Acceso en línea: | https://dx.doi.org/10.1109/TCSI.2019.2944791 http://cds.cern.ch/record/2725891 |