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Real-time cluster finding for LHCb silicon pixel VELO detector using FPGA
In the Run-3 of LHCb, the High Level Trigger will have to process events at full LHC collision rate (30 MHz). This is a very challenging goal, and delegating some low-level tasks to FPGA accelerators can be very helpful by saving precious computing time. In particular, the 2D pixel geometry of the n...
| Autores principales: | , , , , |
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| Lenguaje: | eng |
| Publicado: |
2020
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1088/1742-6596/1525/1/012044 http://cds.cern.ch/record/2744309 |