Real-time cluster finding for LHCb silicon pixel VELO detector using FPGA

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In the Run-3 of LHCb, the High Level Trigger will have to process events at full LHC collision rate (30 MHz). This is a very challenging goal, and delegating some low-level tasks to FPGA accelerators can be very helpful by saving precious computing time. In particular, the 2D pixel geometry of the n...

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Autores principales: Lazzari, Federico, Bassi, Giovanni, Cenci, Riccardo, Morello, Michael J, Punzi, Giovanni
Lenguaje:eng
Publicado: 2020
Materias:
Computing and Computers
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1088/1742-6596/1525/1/012044
http://cds.cern.ch/record/2744309
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author Lazzari, Federico
Bassi, Giovanni
Cenci, Riccardo
Morello, Michael J
Punzi, Giovanni
author_facet Lazzari, Federico
Bassi, Giovanni
Cenci, Riccardo
Morello, Michael J
Punzi, Giovanni
author_sort Lazzari, Federico
collection CERN
description In the Run-3 of LHCb, the High Level Trigger will have to process events at full LHC collision rate (30 MHz). This is a very challenging goal, and delegating some low-level tasks to FPGA accelerators can be very helpful by saving precious computing time. In particular, the 2D pixel geometry of the new LHCb VELO detector makes the cluster-finding process particularly CPU-time demanding. We realized and tested a highly parallel FPGA-based clustering algorithm, capable of performing this reconstruction in real time at 30 MHz event rate using a modest amount of hardware resources, that can be a viable alternative solution.
id oai-inspirehep.net-1806216
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2020
record_format invenio
spelling oai-inspirehep.net-18062162021-02-09T10:07:49Zdoi:10.1088/1742-6596/1525/1/012044http://cds.cern.ch/record/2744309engLazzari, FedericoBassi, GiovanniCenci, RiccardoMorello, Michael JPunzi, GiovanniReal-time cluster finding for LHCb silicon pixel VELO detector using FPGAComputing and ComputersDetectors and Experimental TechniquesIn the Run-3 of LHCb, the High Level Trigger will have to process events at full LHC collision rate (30 MHz). This is a very challenging goal, and delegating some low-level tasks to FPGA accelerators can be very helpful by saving precious computing time. In particular, the 2D pixel geometry of the new LHCb VELO detector makes the cluster-finding process particularly CPU-time demanding. We realized and tested a highly parallel FPGA-based clustering algorithm, capable of performing this reconstruction in real time at 30 MHz event rate using a modest amount of hardware resources, that can be a viable alternative solution.oai:inspirehep.net:18062162020
spellingShingle Computing and Computers
Detectors and Experimental Techniques
Lazzari, Federico
Bassi, Giovanni
Cenci, Riccardo
Morello, Michael J
Punzi, Giovanni
Real-time cluster finding for LHCb silicon pixel VELO detector using FPGA
title Real-time cluster finding for LHCb silicon pixel VELO detector using FPGA
title_full Real-time cluster finding for LHCb silicon pixel VELO detector using FPGA
title_fullStr Real-time cluster finding for LHCb silicon pixel VELO detector using FPGA
title_full_unstemmed Real-time cluster finding for LHCb silicon pixel VELO detector using FPGA
title_short Real-time cluster finding for LHCb silicon pixel VELO detector using FPGA
title_sort real-time cluster finding for lhcb silicon pixel velo detector using fpga
topic Computing and Computers
Detectors and Experimental Techniques
url https://dx.doi.org/10.1088/1742-6596/1525/1/012044
http://cds.cern.ch/record/2744309
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AT bassigiovanni realtimeclusterfindingforlhcbsiliconpixelvelodetectorusingfpga
AT cenciriccardo realtimeclusterfindingforlhcbsiliconpixelvelodetectorusingfpga
AT morellomichaelj realtimeclusterfindingforlhcbsiliconpixelvelodetectorusingfpga
AT punzigiovanni realtimeclusterfindingforlhcbsiliconpixelvelodetectorusingfpga

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