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The front end electronics of the NA62 gigatracker: Challenges, design and experimental measurements
The beam spectrometer of the NA62 experiment consists of 3 Gigatracker (GTK) stations. Each station comprises a pixel detector of 16cm^2 active area made of an assembly of 10 readout ASICs bump bonded to a 200@mm thick pixel silicon sensor, compri sing 18000 pixels of 300@mmx300@mm. The main challen...
Autores principales: | , , , , , , , , , , , , , , , , |
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Lenguaje: | eng |
Publicado: |
2011
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Materias: | |
Acceso en línea: | https://dx.doi.org/10.1016/j.nuclphysbps.2011.04.007 http://cds.cern.ch/record/2002975 |
Sumario: | The beam spectrometer of the NA62 experiment consists of 3 Gigatracker (GTK) stations. Each station comprises a pixel detector of 16cm^2 active area made of an assembly of 10 readout ASICs bump bonded to a 200@mm thick pixel silicon sensor, compri sing 18000 pixels of 300@mmx300@mm. The main challenge of the NA62 pixel GTK station is the combination of an extremely high kaon/pion beam rate, where the intensity in the center of the beam reaches up to 1.5Mhit@?s^-^1mm^-^2 together with an extreme tim e resolution of 100ps. To date, it is the first silicon tracking system with this time resolution. To face this challenge, the pixel analogue front end has been designed with a peaking time of 4ns, with a planar silicon sensor operating up to 300V over de pletion. Moreover, the radiation level is severe, 2x10^1^41MeVn_e_q_.cm^-^2 per year of operation. Easy replacement of the GTK stations is foreseen as a design requirement. The amount of material of a single station should also be less than 0.5% X_0 to mi nimize the background, which imposes strong constraints on the mechanics and the cooling system. We report upon the design and architecture of the 2 prototype demonstrator chips both designed in 130nm CMOS technology, one with a constant fraction discrimi nator and the time stamp digitisation in each pixel (In-Pixel), and the other with a time-over-threshold discriminator and the processing of the time stamp located in the End of Column (EoC) region at the chip periphery. Some preliminary results are prese nted. |
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