Heterogeneous Integration of Atomically‐Thin Indium Tungsten Oxide Transistors for Low‐Power 3D Monolithic Complementary Inverter

In this work, the authors demonstrate a novel vertically‐stacked thin film transistor (TFT) architecture for heterogeneously complementary inverter applications, composed of p‐channel polycrystalline silicon (poly‐Si) and n‐channel amorphous indium tungsten oxide (a‐IWO), with a low footprint than planar structure. The a‐IWO TFT with channel thickness of approximately 3‐4 atomic layers exhibits high mobility of 24 cm(2) V(−1) s(−1), near ideally subthreshold swing of 63 mV dec(−1), low leakage current below 10(−13) A, high on/off current ratio of larger than 10(9), extremely small hysteresis of 0 mV, low contact resistance of 0.44 kΩ‐µm, and high stability after encapsulating a passivation layer. The electrical characteristics of n‐channel a‐IWO TFT are well‐matched with p‐channel poly‐Si TFT for superior complementary metal–oxide‐semiconductor technology applications. The inverter can exhibit a high voltage gain of 152 V V(−1) at low supply voltage of 1.5 V. The noise margin can be up to 80% of supply voltage and perform the symmetrical window. The pico‐watt static power consumption inverter is achieved by the wide energy bandgap of a‐IWO channel and atomically‐thin channel. The vertically‐stacked complementary field‐effect transistors (CFET) with high energy‐efficiency can increase the circuit density in a chip to conform the development of next‐generation semiconductor technology.