Switching performance assessment of gate-all-around InAs–Si vertical TFET with triple metal gate, a simulation study

This study presents a gate-all-around InAs–Si vertical tunnel field-effect transistor with a triple metal gate (VTG-TFET). We obtained improved switching characteristics for the proposed design because of the improved electrostatic control on the channel and the narrow bandgap source. It shows an I(on) of 392 μA/μm, an I(off) of 8.8 × 10(−17) A/μm, an I(on)/I(off) ratio of about 4.4 × 10(12), and a minimum subthreshold slope of 9.3 mV/dec at V(d) = 1 V. We also analyze the influence of the gate oxide and metal work functions on the transistor characteristics. A numerical device simulator, calibrated to the experimental data of a vertical InAs–Si gate all around TFET, is used to accurately predict different features of the device. Our simulations demonstrate that the proposed vertical TFET, as a fast-switching and very low power device, is a promising transistor for digital applications.