Carrier Trap Density Reduction at SiO(2)/4H-Silicon Carbide Interface with Annealing Processes in Phosphoryl Chloride and Nitride Oxide Atmospheres

The electrical and physical properties of the SiC/SiO(2) interfaces are critical for the reliability and performance of SiC-based MOSFETs. Optimizing the oxidation and post-oxidation processes is the most promising method of improving oxide quality, channel mobility, and thus the series resistance of the MOSFET. In this work, we analyze the effects of the POCl(3) annealing and NO annealing processes on the electrical properties of metal–oxide–semiconductor (MOS) devices formed on 4H-SiC (0001). It is shown that combined annealing processes can result in both low interface trap density (D(it)), which is crucial for oxide application in SiC power electronics, and high dielectric breakdown voltage comparable with those obtained via thermal oxidation in pure O(2). Comparative results of non-annealed, NO-annealed, and POCl(3)-annealed oxide–semiconductor structures are shown. POCl(3) annealing reduces the interface state density more effectively than the well-established NO annealing processes. The result of 2 × 10(11) cm(−2) for the interface trap density was attained for a sequence of the two-step annealing process in POCl(3) and next in NO atmospheres. The obtained values D(it) are comparable to the best results for the SiO(2)/4H-SiC structures recognized in the literature, while the dielectric critical field was measured at a level ≥9 MVcm(−1) with low leakage currents at high fields. Dielectrics, which were developed in this study, have been used to fabricate the 4H-SiC MOSFET transistors successfully.