Single event response of ferroelectric spacer engineered SOI FinFET at 14 nm technology node

The impact of spacer on the single event response of SOI FinFET at 14 nm technology node is investigated. Based on the device TCAD model, well-calibrated by the experimental data, it is found that the spacer presents the enhancement on single event transient (SET) compared with no spacer configuration. For single spacer configuration, due to enhanced gate control capability and fringing field, the increments in SET current peak and collected charge for HfO(2) are the least with 2.21%, 0.97%, respectively. Four possible dual ferroelectric spacer configurations are proposed. The placement of ferroelectric spacer at S side and HfO(2) spacer at D side brings to weaken SET with the variation in current peak and collected charge by 6.93%, 1.86%, respectively. The reason may be its enhanced gate controllability over the S/D extension region, which improves the driven current. With linear energy transfer increasing, SET current peak and collected charge present the trend of increase while the bipolar amplification coefficient reduces.