Study of Selective Dry Etching Effects of 15-Cycle Si(0.7)Ge(0.3)/Si Multilayer Structure in Gate-All-Around Transistor Process

Gate-all-around (GAA) structures are important for future logic devices and 3D-DRAM. Inner-spacer cavity etching and channel release both require selective etching of Si(0.7)Ge(0.3). Increasing the number of channel-stacking layers is an effective way to improve device current-driving capability and storage density. Previous work investigated ICP selective etching of a three-cycle Si(0.7)Ge(0.3)/Si multilayer structure and the related etching effects. This study focuses on the dry etching of a 15-cycle Si(0.7)Ge(0.3)/Si multilayer structure and the associated etching effects, using simulation and experimentation. The simulation predicts the random effect of lateral etching depth and the asymmetric effect of silicon nanosheet damage on the edge, both of which are verified by experiments. Furthermore, the study experimentally investigates the influence and mechanism of pressure, power, and other parameters on the etching results. Research on these etching effects and mechanisms will provide important points of reference for the dry selective etching of Si(0.7)Ge(0.3) in GAA structures.