The Characteristics of Seebeck Coefficient in Silicon Nanowires Manufactured by CMOS Compatible Process

Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck...

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Detalles Bibliográficos
Autores principales: Jang, Moongyu, Park, Youngsam, Jun, Myungsim, Hyun, Younghoon, Choi, Sung-Jin, Zyung, Taehyoung
Formato: Texto
Lenguaje:English
Publicado: Springer 2010
Materias:
Nano Express
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC2956042/
https://www.ncbi.nlm.nih.gov/pubmed/21076666
http://dx.doi.org/10.1007/s11671-010-9690-2
Descripción
Sumario:Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck coefficient values are 122 μV/K for p-leg and −94 μV/K for n-leg. The maximum attainable power factor is 0.74 mW/m K(2) at room temperature.

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