PNP PIN bipolar phototransistors for high-speed applications built in a 180 nm CMOS process

This work reports on three speed optimized pnp bipolar phototransistors build in a standard 180 nm CMOS process using a special starting wafer. The starting wafer consists of a low doped p epitaxial layer on top of the p substrate. This low doped p epitaxial layer leads to a thick space-charge regio...

Descripción completa

Detalles Bibliográficos
Autores principales: Kostov, P., Gaberl, W., Hofbauer, M., Zimmermann, H.
Formato: Online Artículo Texto
Lenguaje:English
Publicado: Pergamon Press 2012
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC3587350/
https://www.ncbi.nlm.nih.gov/pubmed/23482349
http://dx.doi.org/10.1016/j.sse.2012.04.011

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC3587350/
https://www.ncbi.nlm.nih.gov/pubmed/23482349
http://dx.doi.org/10.1016/j.sse.2012.04.011

Ejemplares similares