Gold-Free Ternary III–V Antimonide Nanowire Arrays on Silicon: Twin-Free down to the First Bilayer

[Image: see text] With the continued maturation of III–V nanowire research, expectations of material quality should be concomitantly raised. Ideally, III–V nanowires integrated on silicon should be entirely free of extended planar defects such as twins, stacking faults, or polytypism, position-controlled for convenient device processing, and gold-free for compatibility with standard complementary metal–oxide–semiconductor (CMOS) processing tools. Here we demonstrate large area vertical GaAs(x)Sb(1–x) nanowire arrays grown on silicon (111) by molecular beam epitaxy. The nanowires’ complex faceting, pure zinc blende crystal structure, and composition are mapped using characterization techniques both at the nanoscale and in large-area ensembles. We prove unambiguously that these gold-free nanowires are entirely twin-free down to the first bilayer and reveal their three-dimensional composition evolution, paving the way for novel infrared devices integrated directly on the cost-effective Si platform.