The interfaces of lanthanum oxide-based subnanometer EOT gate dielectrics

When pushing the gate dielectric thickness of metal-oxide-semiconductor (MOS) devices down to the subnanometer scale, the most challenging issue is the interface. The interfacial transition layers between the high-k dielectric/Si and between the high-k dielectric/gate metal become the critical constraints for the smallest achievable film thickness. This work presents a detailed study on the interface bonding structures of the tungsten/lanthanum oxide/silicon (W/La(2)O(3)/Si) MOS structure. We found that both W/La(2)O(3) and La(2)O(3)/Si are thermally unstable. Thermal annealing can lead to W oxidation and the forming of a complex oxide layer at the W/La(2)O(3) interface. For the La(2)O(3)/Si interface, thermal annealing leads to a thick low-k silicate layer. These interface layers do not only cause significant device performance degradation, but also impose a limit on the thinnest equivalent oxide thickness (EOT) to be achievable which may be well above the requirements of our future technology nodes.