Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 µm CMOS Process

The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity,...

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Detalles Bibliográficos
Autores principales: Rahman, Labonnah Farzana, Reaz, Mamun Bin Ibne, Yin, Chia Chieu, Ali, Mohammad Alauddin Mohammad, Marufuzzaman, Mohammad
Formato: Online Artículo Texto
Lenguaje:English
Publicado: Public Library of Science 2014
Materias:
Research Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4191981/
https://www.ncbi.nlm.nih.gov/pubmed/25299266
http://dx.doi.org/10.1371/journal.pone.0108634

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4191981/
https://www.ncbi.nlm.nih.gov/pubmed/25299266
http://dx.doi.org/10.1371/journal.pone.0108634

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