Advanced Cu chemical displacement technique for SiO(2)-based electrochemical metallization ReRAM application

This study investigates an advanced copper (Cu) chemical displacement technique (CDT) with varying the chemical displacement time for fabricating Cu/SiO(2)-stacked resistive random-access memory (ReRAM). Compared with other Cu deposition methods, this CDT easily controls the interface of the Cu-insulator, the switching layer thickness, and the immunity of the Cu etching process, assisting the 1-transistor-1-ReRAM (1T-1R) structure and system-on-chip integration. The modulated shape of the Cu-SiO(2) interface and the thickness of the SiO(2) layer obtained by CDT-based Cu deposition on SiO(2) were confirmed by scanning electron microscopy and atomic force microscopy. The CDT-fabricated Cu/SiO(2)-stacked ReRAM exhibited lower operation voltages and more stable data retention characteristics than the control Cu/SiO(2)-stacked sample. As the Cu CDT processing time increased, the forming and set voltages of the CDT-fabricated Cu/SiO(2)-stacked ReRAM decreased. Conversely, decreasing the processing time reduced the on-state current and reset voltage while increasing the endurance switching cycle time. Therefore, the switching characteristics were easily modulated by Cu CDT, yielding a high performance electrochemical metallization (ECM)-type ReRAM.