Electrical characteristic fluctuation of 16-nm-gate high-κ/metal gate bulk FinFET devices in the presence of random interface traps

In this work, we study the impact of random interface traps (RITs) at the interface of SiO( x )/Si on the electrical characteristic of 16-nm-gate high-κ/metal gate (HKMG) bulk fin-type field effect transistor (FinFET) devices. Under the same threshold voltage, the effects of RIT position and number on the degradation of electrical characteristics are clarified with respect to different levels of RIT density of state (D(it)). The variability of the off-state current (I(off)) and drain-induced barrier lowering (DIBL) will be severely affected by RITs with high D(it) varying from 5 × 10(12) to 5 × 10(13) eV(−1) cm(−2) owing to significant threshold voltage (V(th)) fluctuation. The results of this study indicate that if the level of D(it) is lower than 1 × 10(12) eV(−1) cm(−2), the normalized variability of the on-state current, I(off), V(th), DIBL, and subthreshold swing is within 5%.