Hall and field-effect mobilities in few layered p-WSe(2) field-effect transistors

Here, we present a temperature (T) dependent comparison between field-effect and Hall mobilities in field-effect transistors based on few-layered WSe(2) exfoliated onto SiO(2). Without dielectric engineering and beyond a T-dependent threshold gate-voltage, we observe maximum hole mobilities approaching 350 cm(2)/Vs at T = 300 K. The hole Hall mobility reaches a maximum value of 650 cm(2)/Vs as T is lowered below ~150 K, indicating that insofar WSe(2)-based field-effect transistors (FETs) display the largest Hall mobilities among the transition metal dichalcogenides. The gate capacitance, as extracted from the Hall-effect, reveals the presence of spurious charges in the channel, while the two-terminal sheet resistivity displays two-dimensional variable-range hopping behavior, indicating carrier localization induced by disorder at the interface between WSe(2) and SiO(2). We argue that improvements in the fabrication protocols as, for example, the use of a substrate free of dangling bonds are likely to produce WSe(2)-based FETs displaying higher room temperature mobilities, i.e. approaching those of p-doped Si, which would make it a suitable candidate for high performance opto-electronics.