Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure

This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (>1 μA/μm). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier loweri...

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Detalles Bibliográficos
Autores principales: Cheng, Ya-Chi, Chen, Hung-Bin, Su, Jun-Ji, Shao, Chi-Shen, Wang, Cheng-Ping, Chang, Chun-Yen, Wu, Yung-Chun
Formato: Online Artículo Texto
Lenguaje:English
Publicado: Springer-Verlag 2014
Materias:
Nano Express
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4493839/
https://www.ncbi.nlm.nih.gov/pubmed/26089001
http://dx.doi.org/10.1186/1556-276X-9-669

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4493839/
https://www.ncbi.nlm.nih.gov/pubmed/26089001
http://dx.doi.org/10.1186/1556-276X-9-669

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