Cargando…
Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure
This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (>1 μA/μm). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier loweri...
Autores principales: | Cheng, Ya-Chi, Chen, Hung-Bin, Su, Jun-Ji, Shao, Chi-Shen, Wang, Cheng-Ping, Chang, Chun-Yen, Wu, Yung-Chun |
---|---|
Formato: | Online Artículo Texto |
Lenguaje: | English |
Publicado: |
Springer-Verlag
2014
|
Materias: | |
Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4493839/ https://www.ncbi.nlm.nih.gov/pubmed/26089001 http://dx.doi.org/10.1186/1556-276X-9-669 |
Ejemplares similares
-
Temperature dependence of electronic behaviors in quantum dimension junctionless thin-film transistor
por: Cheng, Ya-Chi, et al.
Publicado: (2014) -
A single poly-Si gate-all-around junctionless fin field-effect transistor for use in one-time programming nonvolatile memory
por: Yeh, Mu-Shih, et al.
Publicado: (2014) -
Electrical property comparison and charge transmission in p-type double gate and single gate junctionless accumulation transistor fabricated by AFM nanolithography
por: Dehzangi, Arash, et al.
Publicado: (2012) -
Junctionless ferroelectric field effect transistors based on ultrathin silicon nanomembranes
por: Cao, Ronggen, et al.
Publicado: (2014) -
Junctionless Dual
In-Plane-Gate Thin-Film Transistors
with AND Logic Function on Paper Substrates
por: Dou, Wei, et al.
Publicado: (2019)