Interface Engineering for the Enhancement of Carrier Transport in Black Phosphorus Transistor with Ultra-Thin High-k Gate Dielectric

Black phosphorus (BP) is the most stable allotrope of phosphorus which exhibits strong in-plane anisotropic charge transport. Discovering its interface properties between BP and high-k gate dielectric is fundamentally important for enhancing the carrier mobility and electrostatics control. Here, we investigate the impact of interface engineering on the transport properties of BP transistors with an ultra-thin hafnium-dioxide (HfO(2)) gate dielectric of ~3.4 nm. A high hole mobility of ~536 cm(2)V(−1)s(−1) coupled with a near ideal subthreshold swing (SS) of ~66 mV/dec were simultaneously achieved at room temperature by improving the BP/HfO(2) interface quality through thermal treatment. This is attributed to the passivation of phosphorus dangling bonds by hafnium (Hf) adatoms which produces a more chemically stable interface, as evidenced by the significant reduction in interface states density. Additionally, we found that an excessively high thermal treatment temperature (beyond 200 °C) could detrimentally modify the BP crystal structure, which results in channel resistance and mobility degradation due to charge-impurities scattering and lattice displacement. This study contributes to an insight for the development of high performance BP-based transistors through interface engineering.