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Integration scheme of nanoscale resistive switching memory using bottom-up processes at room temperature for high-density memory applications
A facile and versatile scheme is demonstrated to fabricate nanoscale resistive switching memory devices that exhibit reliable bipolar switching behavior. A solution process is used to synthesize the copper oxide layer into 250-nm via-holes that had been patterned in Si wafers. Direct bottom-up filli...
| Autores principales: | , |
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| Formato: | Online Artículo Texto |
| Lenguaje: | English |
| Publicado: |
Nature Publishing Group
2016
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| Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4929478/ https://www.ncbi.nlm.nih.gov/pubmed/27364856 http://dx.doi.org/10.1038/srep28966 |