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A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme
Minimizing the parasitic capacitance and the number of photo-masks can improve operational speed and reduce fabrication costs. Therefore, in this study, a new two-photo-mask process is proposed that exhibits a self-aligned structure without an etching-stop layer. Combining the backside-ultraviolet (...
Autores principales: | , , , , , |
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Formato: | Online Artículo Texto |
Lenguaje: | English |
Publicado: |
MDPI
2014
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Materias: | |
Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5456189/ https://www.ncbi.nlm.nih.gov/pubmed/28788159 http://dx.doi.org/10.3390/ma7085761 |
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author | Fan, Ching-Lin Shang, Ming-Chi Li, Bo-Jyun Lin, Yu-Zuo Wang, Shea-Jue Lee, Win-Der |
author_facet | Fan, Ching-Lin Shang, Ming-Chi Li, Bo-Jyun Lin, Yu-Zuo Wang, Shea-Jue Lee, Win-Der |
author_sort | Fan, Ching-Lin |
collection | PubMed |
description | Minimizing the parasitic capacitance and the number of photo-masks can improve operational speed and reduce fabrication costs. Therefore, in this study, a new two-photo-mask process is proposed that exhibits a self-aligned structure without an etching-stop layer. Combining the backside-ultraviolet (BUV) exposure and backside-lift-off (BLO) schemes can not only prevent the damage when etching the source/drain (S/D) electrodes but also reduce the number of photo-masks required during fabrication and minimize the parasitic capacitance with the decreasing of gate overlap length at same time. Compared with traditional fabrication processes, the proposed process yields that thin-film transistors (TFTs) exhibit comparable field-effect mobility (9.5 cm(2)/V·s), threshold voltage (3.39 V), and subthreshold swing (0.3 V/decade). The delay time of an inverter fabricated using the proposed process was considerably decreased. |
format | Online Article Text |
id | pubmed-5456189 |
institution | National Center for Biotechnology Information |
language | English |
publishDate | 2014 |
publisher | MDPI |
record_format | MEDLINE/PubMed |
spelling | pubmed-54561892017-07-28 A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme Fan, Ching-Lin Shang, Ming-Chi Li, Bo-Jyun Lin, Yu-Zuo Wang, Shea-Jue Lee, Win-Der Materials (Basel) Article Minimizing the parasitic capacitance and the number of photo-masks can improve operational speed and reduce fabrication costs. Therefore, in this study, a new two-photo-mask process is proposed that exhibits a self-aligned structure without an etching-stop layer. Combining the backside-ultraviolet (BUV) exposure and backside-lift-off (BLO) schemes can not only prevent the damage when etching the source/drain (S/D) electrodes but also reduce the number of photo-masks required during fabrication and minimize the parasitic capacitance with the decreasing of gate overlap length at same time. Compared with traditional fabrication processes, the proposed process yields that thin-film transistors (TFTs) exhibit comparable field-effect mobility (9.5 cm(2)/V·s), threshold voltage (3.39 V), and subthreshold swing (0.3 V/decade). The delay time of an inverter fabricated using the proposed process was considerably decreased. MDPI 2014-08-11 /pmc/articles/PMC5456189/ /pubmed/28788159 http://dx.doi.org/10.3390/ma7085761 Text en © 2014 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution license (http://creativecommons.org/licenses/by/3.0/). |
spellingShingle | Article Fan, Ching-Lin Shang, Ming-Chi Li, Bo-Jyun Lin, Yu-Zuo Wang, Shea-Jue Lee, Win-Der A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme |
title | A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme |
title_full | A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme |
title_fullStr | A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme |
title_full_unstemmed | A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme |
title_short | A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme |
title_sort | self-aligned a-igzo thin-film transistor using a new two-photo-mask process with a continuous etching scheme |
topic | Article |
url | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5456189/ https://www.ncbi.nlm.nih.gov/pubmed/28788159 http://dx.doi.org/10.3390/ma7085761 |
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