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Failure Analysis in Magnetic Tunnel Junction Nanopillar with Interfacial Perpendicular Magnetic Anisotropy

Magnetic tunnel junction nanopillar with interfacial perpendicular magnetic anisotropy (PMA-MTJ) becomes a promising candidate to build up spin transfer torque magnetic random access memory (STT-MRAM) for the next generation of non-volatile memory as it features low spin transfer switching current,...

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Detalles Bibliográficos
Autores principales: Zhao, Weisheng, Zhao, Xiaoxuan, Zhang, Boyu, Cao, Kaihua, Wang, Lezhi, Kang, Wang, Shi, Qian, Wang, Mengxing, Zhang, Yu, Wang, You, Peng, Shouzhong, Klein, Jacques-Olivier, de Barros Naviner, Lirida Alves, Ravelosona, Dafine
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2016
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5456535/
https://www.ncbi.nlm.nih.gov/pubmed/28787842
http://dx.doi.org/10.3390/ma9010041
Descripción
Sumario:Magnetic tunnel junction nanopillar with interfacial perpendicular magnetic anisotropy (PMA-MTJ) becomes a promising candidate to build up spin transfer torque magnetic random access memory (STT-MRAM) for the next generation of non-volatile memory as it features low spin transfer switching current, fast speed, high scalability, and easy integration into conventional complementary metal oxide semiconductor (CMOS) circuits. However, this device suffers from a number of failure issues, such as large process variation and tunneling barrier breakdown. The large process variation is an intrinsic issue for PMA-MTJ as it is based on the interfacial effects between ultra-thin films with few layers of atoms; the tunneling barrier breakdown is due to the requirement of an ultra-thin tunneling barrier (e.g., <1 nm) to reduce the resistance area for the spin transfer torque switching in the nanopillar. These failure issues limit the research and development of STT-MRAM to widely achieve commercial products. In this paper, we give a full analysis of failure mechanisms for PMA-MTJ and present some eventual solutions from device fabrication to system level integration to optimize the failure issues.