A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process

This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application. With compact cell area and full logic compatibility, this new nv-SRAM incorporates two STI-ReRAMs e...

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Detalles Bibliográficos
Autores principales: Hsu, Meng-Yin, Liao, Chu-Feng, Shih, Yi-Hong, Lin, Chrong Jung, King, Ya-Chin
Formato: Online Artículo Texto
Lenguaje:English
Publicado: Springer US 2017
Materias:
Nano Express
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5472634/
https://www.ncbi.nlm.nih.gov/pubmed/28622720
http://dx.doi.org/10.1186/s11671-017-2191-9

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5472634/
https://www.ncbi.nlm.nih.gov/pubmed/28622720
http://dx.doi.org/10.1186/s11671-017-2191-9

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