A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process

This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application. With compact cell area and full logic compatibility, this new nv-SRAM incorporates two STI-ReRAMs e...

Descripción completa

Detalles Bibliográficos
Autores principales: Hsu, Meng-Yin, Liao, Chu-Feng, Shih, Yi-Hong, Lin, Chrong Jung, King, Ya-Chin
Formato: Online Artículo Texto
Lenguaje:English
Publicado: Springer US 2017
Materias:
Nano Express
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5472634/
https://www.ncbi.nlm.nih.gov/pubmed/28622720
http://dx.doi.org/10.1186/s11671-017-2191-9
_version_ 1783244148234518528
author Hsu, Meng-Yin
Liao, Chu-Feng
Shih, Yi-Hong
Lin, Chrong Jung
King, Ya-Chin
author_facet Hsu, Meng-Yin
Liao, Chu-Feng
Shih, Yi-Hong
Lin, Chrong Jung
King, Ya-Chin
author_sort Hsu, Meng-Yin
collection PubMed
description This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application. With compact cell area and full logic compatibility, this new nv-SRAM incorporates two STI-ReRAMs embedded inside the 4T SRAM. Data can be read/write through a cross-couple volatile structure for maintaining fast accessing speed. Data can be non-volatilely stored in new SRAM cell through a unique self-inhibit operation onto the resistive random access memory (RRAM) load, achieving zero static power during data hold.
format Online
Article
Text
id pubmed-5472634
institution National Center for Biotechnology Information
language English
publishDate 2017
publisher Springer US
record_format MEDLINE/PubMed
spelling pubmed-54726342017-06-28 A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process Hsu, Meng-Yin Liao, Chu-Feng Shih, Yi-Hong Lin, Chrong Jung King, Ya-Chin Nanoscale Res Lett Nano Express This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application. With compact cell area and full logic compatibility, this new nv-SRAM incorporates two STI-ReRAMs embedded inside the 4T SRAM. Data can be read/write through a cross-couple volatile structure for maintaining fast accessing speed. Data can be non-volatilely stored in new SRAM cell through a unique self-inhibit operation onto the resistive random access memory (RRAM) load, achieving zero static power during data hold. Springer US 2017-06-15 /pmc/articles/PMC5472634/ /pubmed/28622720 http://dx.doi.org/10.1186/s11671-017-2191-9 Text en © The Author(s). 2017 Open AccessThis article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.
spellingShingle Nano Express
Hsu, Meng-Yin
Liao, Chu-Feng
Shih, Yi-Hong
Lin, Chrong Jung
King, Ya-Chin
A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process
title A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process
title_full A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process
title_fullStr A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process
title_full_unstemmed A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process
title_short A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process
title_sort rram integrated 4t sram with self-inhibit resistive switching load by pure cmos logic process
topic Nano Express
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5472634/
https://www.ncbi.nlm.nih.gov/pubmed/28622720
http://dx.doi.org/10.1186/s11671-017-2191-9
work_keys_str_mv AT hsumengyin arramintegrated4tsramwithselfinhibitresistiveswitchingloadbypurecmoslogicprocess
AT liaochufeng arramintegrated4tsramwithselfinhibitresistiveswitchingloadbypurecmoslogicprocess
AT shihyihong arramintegrated4tsramwithselfinhibitresistiveswitchingloadbypurecmoslogicprocess
AT linchrongjung arramintegrated4tsramwithselfinhibitresistiveswitchingloadbypurecmoslogicprocess
AT kingyachin arramintegrated4tsramwithselfinhibitresistiveswitchingloadbypurecmoslogicprocess
AT hsumengyin rramintegrated4tsramwithselfinhibitresistiveswitchingloadbypurecmoslogicprocess
AT liaochufeng rramintegrated4tsramwithselfinhibitresistiveswitchingloadbypurecmoslogicprocess
AT shihyihong rramintegrated4tsramwithselfinhibitresistiveswitchingloadbypurecmoslogicprocess
AT linchrongjung rramintegrated4tsramwithselfinhibitresistiveswitchingloadbypurecmoslogicprocess
AT kingyachin rramintegrated4tsramwithselfinhibitresistiveswitchingloadbypurecmoslogicprocess

Ejemplares similares