A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel †

A submicron pixel’s light and dark performance were studied by experiment and simulation. An advanced node technology incorporated with a stacked CMOS image sensor (CIS) is promising in that it may enhance performance. In this work, we demonstrated a low dark current of 3.2 e(−)/s at 60 °C, an ultra-low read noise of 0.90 e(−)·rms, a high full well capacity (FWC) of 4100 e(−), and blooming of 0.5% in 0.9 μm pixels with a pixel supply voltage of 2.8 V. In addition, the simulation study result of 0.8 μm pixels is discussed.