Gate Tunable Transport in Graphene/MoS(2)/(Cr/Au) Vertical Field-Effect Transistors

Two-dimensional materials based vertical field-effect transistors have been widely studied due to their useful applications in industry. In the present study, we fabricate graphene/MoS(2)/(Cr/Au) vertical transistor based on the mechanical exfoliation and dry transfer method. Since the bottom electrode was made of monolayer graphene (Gr), the electrical transport in our Gr/MoS(2)/(Cr/Au) vertical transistors can be significantly modified by using back-gate voltage. Schottky barrier height at the interface between Gr and MoS(2) can be modified by back-gate voltage and the current bias. Vertical resistance (R(vert)) of a Gr/MoS(2)/(Cr/Au) transistor is compared with planar resistance (R(planar)) of a conventional lateral MoS(2) field-effect transistor. We have also studied electrical properties for various thicknesses of MoS(2) channels in both vertical and lateral transistors. As the thickness of MoS(2) increases, R(vert) increases, but R(planar) decreases. The increase of R(vert) in the thicker MoS(2) film is attributed to the interlayer resistance in the vertical direction. However, R(planar) shows a lower value for a thicker MoS(2) film because of an excess of charge carriers available in upper layers connected directly to source/drain contacts that limits the conduction through layers closed to source/drain electrodes. Hence, interlayer resistance associated with these layers contributes to planer resistance in contrast to vertical devices in which all layers contribute interlayer resistance.