The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

The DRAM based on the dual-gate tunneling FET (DGTFET) has the advantages of capacitor-less structure and high retention time. In this paper, the optimization of spacer engineering for DGTFET DRAM is systematically investigated by Silvaco-Atlas tool to further improve its performance, including the...

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Detalles Bibliográficos
Autores principales: Li, Wei, Liu, Hongxia, Wang, Shulong, Chen, Shupeng, Wang, Qianqiong
Formato: Online Artículo Texto
Lenguaje:English
Publicado: Springer US 2018
Materias:
Nano Express
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5838025/
https://www.ncbi.nlm.nih.gov/pubmed/29508093
http://dx.doi.org/10.1186/s11671-018-2483-8

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5838025/
https://www.ncbi.nlm.nih.gov/pubmed/29508093
http://dx.doi.org/10.1186/s11671-018-2483-8

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