The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

The DRAM based on the dual-gate tunneling FET (DGTFET) has the advantages of capacitor-less structure and high retention time. In this paper, the optimization of spacer engineering for DGTFET DRAM is systematically investigated by Silvaco-Atlas tool to further improve its performance, including the reduction of reading “0” current and extension of retention time. The simulation results show that spacers at the source and drain sides should apply the low-k and high-k dielectrics, respectively, which can enhance the reading “1” current and reduce reading “0” current. Applying this optimized spacer engineering, the DGTFET DRAM obtains the optimum performance-extremely low reading “0” current (10(−14)A/μm) and large retention time (10s), which decreases its static power consumption and dynamic refresh rate. And the low reading “0” current also enhances its current ratio (10(7)) of reading “1” to reading “0”. Furthermore, the analysis about scalability reveals its inherent shortcoming, which offers the further investigation direction for DGTFET DRAM.