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A shared synapse architecture for efficient FPGA implementation of autoencoders
This paper proposes a shared synapse architecture for autoencoders (AEs), and implements an AE with the proposed architecture as a digital circuit on a field-programmable gate array (FPGA). In the proposed architecture, the values of the synapse weights are shared between the synapses of an input an...
| Autores principales: | , , |
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| Formato: | Online Artículo Texto |
| Lenguaje: | English |
| Publicado: |
Public Library of Science
2018
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| Materias: | |
| Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5854352/ https://www.ncbi.nlm.nih.gov/pubmed/29543909 http://dx.doi.org/10.1371/journal.pone.0194049 |