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InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities
III-V semiconductors are being considered as promising candidates to replace silicon channel for low-power logic and RF applications in advanced technology nodes. InGaAs is particularly suitable as the channel material in n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), due to it...
Autores principales: | , , , , , , |
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Formato: | Online Artículo Texto |
Lenguaje: | English |
Publicado: |
MDPI
2018
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Materias: | |
Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6337424/ https://www.ncbi.nlm.nih.gov/pubmed/30591676 http://dx.doi.org/10.3390/ma12010087 |
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author | Convertino, Clarissa Zota, Cezar Schmid, Heinz Caimi, Daniele Sousa, Marilyne Moselund, Kirsten Czornomaz, Lukas |
author_facet | Convertino, Clarissa Zota, Cezar Schmid, Heinz Caimi, Daniele Sousa, Marilyne Moselund, Kirsten Czornomaz, Lukas |
author_sort | Convertino, Clarissa |
collection | PubMed |
description | III-V semiconductors are being considered as promising candidates to replace silicon channel for low-power logic and RF applications in advanced technology nodes. InGaAs is particularly suitable as the channel material in n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), due to its high electron mobility. In the present work, we report on InGaAs FinFETs monolithically integrated on silicon substrates. The InGaAs channels are created by metal–organic chemical vapor deposition (MOCVD) epitaxial growth within oxide cavities, a technique referred to as template-assisted selective epitaxy (TASE), which allows for the local integration of different III-V semiconductors on silicon. FinFETs with a gate length down to 20nm are fabricated based on a CMOS-compatible replacement-metal-gate process flow. This includes self-aligned source-drain n(+) InGaAs regrown contacts as well as 4 nm source-drain spacers for gate-contacts isolation. The InGaAs material was examined by scanning transmission electron microscopy (STEM) and the epitaxial structures showed good crystal quality. Furthermore, we demonstrate a controlled InGaAs digital etching process to create doped extensions underneath the source-drain spacer regions. We report a device with gate length of 90 nm and fin width of 40 nm showing on-current of 100 µA/µm and subthreshold slope of about 85 mV/dec. |
format | Online Article Text |
id | pubmed-6337424 |
institution | National Center for Biotechnology Information |
language | English |
publishDate | 2018 |
publisher | MDPI |
record_format | MEDLINE/PubMed |
spelling | pubmed-63374242019-01-22 InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities Convertino, Clarissa Zota, Cezar Schmid, Heinz Caimi, Daniele Sousa, Marilyne Moselund, Kirsten Czornomaz, Lukas Materials (Basel) Article III-V semiconductors are being considered as promising candidates to replace silicon channel for low-power logic and RF applications in advanced technology nodes. InGaAs is particularly suitable as the channel material in n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), due to its high electron mobility. In the present work, we report on InGaAs FinFETs monolithically integrated on silicon substrates. The InGaAs channels are created by metal–organic chemical vapor deposition (MOCVD) epitaxial growth within oxide cavities, a technique referred to as template-assisted selective epitaxy (TASE), which allows for the local integration of different III-V semiconductors on silicon. FinFETs with a gate length down to 20nm are fabricated based on a CMOS-compatible replacement-metal-gate process flow. This includes self-aligned source-drain n(+) InGaAs regrown contacts as well as 4 nm source-drain spacers for gate-contacts isolation. The InGaAs material was examined by scanning transmission electron microscopy (STEM) and the epitaxial structures showed good crystal quality. Furthermore, we demonstrate a controlled InGaAs digital etching process to create doped extensions underneath the source-drain spacer regions. We report a device with gate length of 90 nm and fin width of 40 nm showing on-current of 100 µA/µm and subthreshold slope of about 85 mV/dec. MDPI 2018-12-27 /pmc/articles/PMC6337424/ /pubmed/30591676 http://dx.doi.org/10.3390/ma12010087 Text en © 2018 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/). |
spellingShingle | Article Convertino, Clarissa Zota, Cezar Schmid, Heinz Caimi, Daniele Sousa, Marilyne Moselund, Kirsten Czornomaz, Lukas InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities |
title | InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities |
title_full | InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities |
title_fullStr | InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities |
title_full_unstemmed | InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities |
title_short | InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities |
title_sort | ingaas finfets directly integrated on silicon by selective growth in oxide cavities |
topic | Article |
url | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6337424/ https://www.ncbi.nlm.nih.gov/pubmed/30591676 http://dx.doi.org/10.3390/ma12010087 |
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