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Nanoimprint lithography steppers for volume fabrication of leading-edge semiconductor integrated circuits

This article discusses the transition of a form of nanoimprint lithography technology, known as Jet and Flash Imprint Lithography (J-FIL), from research to a commercial fabrication infrastructure for leading-edge semiconductor integrated circuits (ICs). Leading-edge semiconductor lithography has som...

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Autor principal: Sreenivasan, S.V.
Formato: Online Artículo Texto
Lenguaje:English
Publicado: Nature Publishing Group 2017
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6445000/
https://www.ncbi.nlm.nih.gov/pubmed/31057889
http://dx.doi.org/10.1038/micronano.2017.75
_version_ 1783408117459976192
author Sreenivasan, S.V.
author_facet Sreenivasan, S.V.
author_sort Sreenivasan, S.V.
collection PubMed
description This article discusses the transition of a form of nanoimprint lithography technology, known as Jet and Flash Imprint Lithography (J-FIL), from research to a commercial fabrication infrastructure for leading-edge semiconductor integrated circuits (ICs). Leading-edge semiconductor lithography has some of the most aggressive technology requirements, and has been a key driver in the 50-year history of semiconductor scaling. Introducing a new, disruptive capability into this arena is therefore a case study in a “high-risk-high-reward” opportunity. This article first discusses relevant literature in nanopatterning including advanced lithography options that have been explored by the IC fabrication industry, novel research ideas being explored, and literature in nanoimprint lithography. The article then focuses on the J-FIL process, and the interdisciplinary nature of risk, involving nanoscale precision systems, mechanics, materials, material delivery systems, contamination control, and process engineering. Next, the article discusses the strategic decisions that were made in the early phases of the project including: (i) choosing a step and repeat process approach; (ii) identifying the first target IC market for J-FIL; (iii) defining the product scope and the appropriate collaborations to share the risk-reward landscape; and (iv) properly leveraging existing infrastructure, including minimizing disruption to the widely accepted practices in photolithography. Finally, the paper discusses the commercial J-FIL stepper system and associated infrastructure, and the resulting advances in the key lithographic process metrics such as critical dimension control, overlay, throughput, process defects, and electrical yield over the past 5 years. This article concludes with the current state of the art in J-FIL technology for IC fabrication, including description of the high volume manufacturing stepper tools created for advanced memory manufacturing.
format Online
Article
Text
id pubmed-6445000
institution National Center for Biotechnology Information
language English
publishDate 2017
publisher Nature Publishing Group
record_format MEDLINE/PubMed
spelling pubmed-64450002019-05-03 Nanoimprint lithography steppers for volume fabrication of leading-edge semiconductor integrated circuits Sreenivasan, S.V. Microsyst Nanoeng Review Article This article discusses the transition of a form of nanoimprint lithography technology, known as Jet and Flash Imprint Lithography (J-FIL), from research to a commercial fabrication infrastructure for leading-edge semiconductor integrated circuits (ICs). Leading-edge semiconductor lithography has some of the most aggressive technology requirements, and has been a key driver in the 50-year history of semiconductor scaling. Introducing a new, disruptive capability into this arena is therefore a case study in a “high-risk-high-reward” opportunity. This article first discusses relevant literature in nanopatterning including advanced lithography options that have been explored by the IC fabrication industry, novel research ideas being explored, and literature in nanoimprint lithography. The article then focuses on the J-FIL process, and the interdisciplinary nature of risk, involving nanoscale precision systems, mechanics, materials, material delivery systems, contamination control, and process engineering. Next, the article discusses the strategic decisions that were made in the early phases of the project including: (i) choosing a step and repeat process approach; (ii) identifying the first target IC market for J-FIL; (iii) defining the product scope and the appropriate collaborations to share the risk-reward landscape; and (iv) properly leveraging existing infrastructure, including minimizing disruption to the widely accepted practices in photolithography. Finally, the paper discusses the commercial J-FIL stepper system and associated infrastructure, and the resulting advances in the key lithographic process metrics such as critical dimension control, overlay, throughput, process defects, and electrical yield over the past 5 years. This article concludes with the current state of the art in J-FIL technology for IC fabrication, including description of the high volume manufacturing stepper tools created for advanced memory manufacturing. Nature Publishing Group 2017-09-25 /pmc/articles/PMC6445000/ /pubmed/31057889 http://dx.doi.org/10.1038/micronano.2017.75 Text en Copyright © 2017 The Author(s) http://creativecommons.org/licenses/by/4.0/ This work is licensed under a Creative Commons Attribution 4.0 International License. The images or other third party material in this article are included in the article’s Creative Commons license, unless indicated otherwise in the credit line; if the material is not included under the Creative Commons license, users will need to obtain permission from the license holder to reproduce the material. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/
spellingShingle Review Article
Sreenivasan, S.V.
Nanoimprint lithography steppers for volume fabrication of leading-edge semiconductor integrated circuits
title Nanoimprint lithography steppers for volume fabrication of leading-edge semiconductor integrated circuits
title_full Nanoimprint lithography steppers for volume fabrication of leading-edge semiconductor integrated circuits
title_fullStr Nanoimprint lithography steppers for volume fabrication of leading-edge semiconductor integrated circuits
title_full_unstemmed Nanoimprint lithography steppers for volume fabrication of leading-edge semiconductor integrated circuits
title_short Nanoimprint lithography steppers for volume fabrication of leading-edge semiconductor integrated circuits
title_sort nanoimprint lithography steppers for volume fabrication of leading-edge semiconductor integrated circuits
topic Review Article
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6445000/
https://www.ncbi.nlm.nih.gov/pubmed/31057889
http://dx.doi.org/10.1038/micronano.2017.75
work_keys_str_mv AT sreenivasansv nanoimprintlithographysteppersforvolumefabricationofleadingedgesemiconductorintegratedcircuits