Tight Evaluation of Real-Time Task Schedulability for Processor’s DVS and Nonvolatile Memory Allocation

A power-saving approach for real-time systems that combines processor voltage scaling and task placement in hybrid memory is presented. The proposed approach incorporates the task’s memory placement problem between the DRAM (dynamic random access memory) and NVRAM (nonvolatile random access memory)...

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Detalles Bibliográficos
Autores principales: Nam, Sunhwa A., Cho, Kyungwoon, Bahn, Hyokyung
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2019
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6630831/
https://www.ncbi.nlm.nih.gov/pubmed/31163692
http://dx.doi.org/10.3390/mi10060371

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6630831/
https://www.ncbi.nlm.nih.gov/pubmed/31163692
http://dx.doi.org/10.3390/mi10060371

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