A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs

An in-house-built three-dimensional multi-method semi-classical/classical toolbox has been developed to characterise the performance, scalability, and variability of state-of-the-art semiconductor devices. To demonstrate capabilities of the toolbox, a 10 nm gate length Si gate-all-around field-effect transistor is selected as a benchmark device. The device exhibits an off-current ([Formula: see text]) of [Formula: see text] [Formula: see text] A/ [Formula: see text] m, and an on-current ([Formula: see text]) of 1770 [Formula: see text] A/ [Formula: see text] m, with the [Formula: see text] ratio [Formula: see text] , a value [Formula: see text] larger than that of a [Formula: see text] nm gate length Si FinFET. The device SS is 71 mV/dec, no far from the ideal limit of 60 mV/dec. The threshold voltage standard deviation due to statistical combination of four sources of variability (line- and gate-edge roughness, metal grain granularity, and random dopants) is [Formula: see text] mV, a value noticeably larger than that of the equivalent FinFET (30 mV). Finally, using a fluctuation sensitivity map, we establish which regions of the device are the most sensitive to the line-edge roughness and the metal grain granularity variability effects. The on-current of the device is strongly affected by any line-edge roughness taking place near the source-gate junction or by metal grains localised between the middle of the gate and the proximity of the gate-source junction.