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Shape-controlled single-crystal growth of InP at low temperatures down to 220 °C

III–V compound semiconductors are widely used for electronic and optoelectronic applications. However, interfacing III–Vs with other materials has been fundamentally limited by the high growth temperatures and lattice-match requirements of traditional deposition processes. Recently, we developed the...

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Autores principales: Hettick, Mark, Li, Hao, Lien, Der-Hsien, Yeh, Matthew, Yang, Tzu-Yi, Amani, Matin, Gupta, Niharika, Chrzan, Daryl C., Chueh, Yu-Lun, Javey, Ali
Formato: Online Artículo Texto
Lenguaje:English
Publicado: National Academy of Sciences 2020
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6969534/
https://www.ncbi.nlm.nih.gov/pubmed/31892540
http://dx.doi.org/10.1073/pnas.1915786117
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author Hettick, Mark
Li, Hao
Lien, Der-Hsien
Yeh, Matthew
Yang, Tzu-Yi
Amani, Matin
Gupta, Niharika
Chrzan, Daryl C.
Chueh, Yu-Lun
Javey, Ali
author_facet Hettick, Mark
Li, Hao
Lien, Der-Hsien
Yeh, Matthew
Yang, Tzu-Yi
Amani, Matin
Gupta, Niharika
Chrzan, Daryl C.
Chueh, Yu-Lun
Javey, Ali
author_sort Hettick, Mark
collection PubMed
description III–V compound semiconductors are widely used for electronic and optoelectronic applications. However, interfacing III–Vs with other materials has been fundamentally limited by the high growth temperatures and lattice-match requirements of traditional deposition processes. Recently, we developed the templated liquid-phase (TLP) crystal growth method for enabling direct growth of shape-controlled single-crystal III-Vs on amorphous substrates. Although in theory, the lowest temperature for TLP growth is that of the melting point of the group III metal (e.g., 156.6 °C for indium), previous experiments required a minimum growth temperature of 500 °C, thus being incompatible with many application-specific substrates. Here, we demonstrate low-temperature TLP (LT-TLP) growth of single-crystalline InP patterns at substrate temperatures down to 220 °C by first activating the precursor, thus enabling the direct growth of InP even on low thermal budget substrates such as plastics and indium-tin-oxide (ITO)–coated glass. Importantly, the material exhibits high electron mobilities and good optoelectronic properties as demonstrated by the fabrication of high-performance transistors and light-emitting devices. Furthermore, this work may enable integration of III–Vs with silicon complementary metal-oxide-semiconductor (CMOS) processing for monolithic 3D integrated circuits and/or back-end electronics.
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spelling pubmed-69695342020-01-27 Shape-controlled single-crystal growth of InP at low temperatures down to 220 °C Hettick, Mark Li, Hao Lien, Der-Hsien Yeh, Matthew Yang, Tzu-Yi Amani, Matin Gupta, Niharika Chrzan, Daryl C. Chueh, Yu-Lun Javey, Ali Proc Natl Acad Sci U S A Physical Sciences III–V compound semiconductors are widely used for electronic and optoelectronic applications. However, interfacing III–Vs with other materials has been fundamentally limited by the high growth temperatures and lattice-match requirements of traditional deposition processes. Recently, we developed the templated liquid-phase (TLP) crystal growth method for enabling direct growth of shape-controlled single-crystal III-Vs on amorphous substrates. Although in theory, the lowest temperature for TLP growth is that of the melting point of the group III metal (e.g., 156.6 °C for indium), previous experiments required a minimum growth temperature of 500 °C, thus being incompatible with many application-specific substrates. Here, we demonstrate low-temperature TLP (LT-TLP) growth of single-crystalline InP patterns at substrate temperatures down to 220 °C by first activating the precursor, thus enabling the direct growth of InP even on low thermal budget substrates such as plastics and indium-tin-oxide (ITO)–coated glass. Importantly, the material exhibits high electron mobilities and good optoelectronic properties as demonstrated by the fabrication of high-performance transistors and light-emitting devices. Furthermore, this work may enable integration of III–Vs with silicon complementary metal-oxide-semiconductor (CMOS) processing for monolithic 3D integrated circuits and/or back-end electronics. National Academy of Sciences 2020-01-14 2019-12-31 /pmc/articles/PMC6969534/ /pubmed/31892540 http://dx.doi.org/10.1073/pnas.1915786117 Text en Copyright © 2020 the Author(s). Published by PNAS. https://creativecommons.org/licenses/by-nc-nd/4.0/ https://creativecommons.org/licenses/by-nc-nd/4.0/This open access article is distributed under Creative Commons Attribution-NonCommercial-NoDerivatives License 4.0 (CC BY-NC-ND) (https://creativecommons.org/licenses/by-nc-nd/4.0/) .
spellingShingle Physical Sciences
Hettick, Mark
Li, Hao
Lien, Der-Hsien
Yeh, Matthew
Yang, Tzu-Yi
Amani, Matin
Gupta, Niharika
Chrzan, Daryl C.
Chueh, Yu-Lun
Javey, Ali
Shape-controlled single-crystal growth of InP at low temperatures down to 220 °C
title Shape-controlled single-crystal growth of InP at low temperatures down to 220 °C
title_full Shape-controlled single-crystal growth of InP at low temperatures down to 220 °C
title_fullStr Shape-controlled single-crystal growth of InP at low temperatures down to 220 °C
title_full_unstemmed Shape-controlled single-crystal growth of InP at low temperatures down to 220 °C
title_short Shape-controlled single-crystal growth of InP at low temperatures down to 220 °C
title_sort shape-controlled single-crystal growth of inp at low temperatures down to 220 °c
topic Physical Sciences
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6969534/
https://www.ncbi.nlm.nih.gov/pubmed/31892540
http://dx.doi.org/10.1073/pnas.1915786117
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