Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices

This paper reports on the optimization of the device and wiring in a via structure applied to multilevel metallization (MLM) used in CMOS logic devices. A MLM via can be applied to the Tungsten (W) plug process of the logic device by following the most optimized barrier deposition scheme of RF etchi...

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Detalles Bibliográficos
Autores principales: Cui, Yinhua, Jeong, Jeong Yeul, Gao, Yuan, Pyo, Sung Gyu
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2019
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7019522/
https://www.ncbi.nlm.nih.gov/pubmed/31881782
http://dx.doi.org/10.3390/mi11010032

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7019522/
https://www.ncbi.nlm.nih.gov/pubmed/31881782
http://dx.doi.org/10.3390/mi11010032

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