Reducing the WCET and analysis time of systems with simple lockable instruction caches

One of the key challenges in real-time systems is the analysis of the memory hierarchy. Many Worst-Case Execution Time (WCET) analysis methods supporting an instruction cache are based on iterative or convergence algorithms, which are rather slow. Our goal in this paper is to reduce the WCET analysi...

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Detalles Bibliográficos
Autores principales: Pedro-Zapater, Alba, Segarra, Juan, Gran Tejero, Rubén, Viñals, Víctor, Rodríguez, Clemente
Formato: Online Artículo Texto
Lenguaje:English
Publicado: Public Library of Science 2020
Materias:
Research Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7082033/
https://www.ncbi.nlm.nih.gov/pubmed/32191731
http://dx.doi.org/10.1371/journal.pone.0229980

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7082033/
https://www.ncbi.nlm.nih.gov/pubmed/32191731
http://dx.doi.org/10.1371/journal.pone.0229980

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