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An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction

This paper presented a non-uniform multiphase (NUMP) time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA) with real-time automatic temperature compensation. NUMP-TDC is a novel, low-cost, high-performance TDC that has achieved an excellent performance in Altera Cyclo...

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Autores principales: Song, Zhipeng, Zhao, Zhixiang, Yu, Hongsen, Yang, Jingwu, Zhang, Xi, Sui, Tengjie, Xu, Jianfeng, Xie, Siwei, Huang, Qiu, Peng, Qiyu
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2020
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7218734/
https://www.ncbi.nlm.nih.gov/pubmed/32290511
http://dx.doi.org/10.3390/s20082172
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author Song, Zhipeng
Zhao, Zhixiang
Yu, Hongsen
Yang, Jingwu
Zhang, Xi
Sui, Tengjie
Xu, Jianfeng
Xie, Siwei
Huang, Qiu
Peng, Qiyu
author_facet Song, Zhipeng
Zhao, Zhixiang
Yu, Hongsen
Yang, Jingwu
Zhang, Xi
Sui, Tengjie
Xu, Jianfeng
Xie, Siwei
Huang, Qiu
Peng, Qiyu
author_sort Song, Zhipeng
collection PubMed
description This paper presented a non-uniform multiphase (NUMP) time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA) with real-time automatic temperature compensation. NUMP-TDC is a novel, low-cost, high-performance TDC that has achieved an excellent performance in Altera Cyclone V FPGA. The root mean square (RMS) for the intrinsic timing resolution was 2.3 ps. However, the propagation delays in the delay chain of some FPGAs (for example, the Altera Cyclone 10 LP) vary significantly as the temperature changes. Thus, the timing performances of NUMP-TDCs implemented in those FPGAs are significantly impacted by temperature fluctuations. In this study, a simple method was developed to monitor variations in propagation delays using two registers deployed at both ends of the delay chain and compensate for changes in propagation delay using a look-up table (LUT). When the variations exceeded a certain threshold, the LUT for the delay correction was updated, and a bin-by-bin correction was launched. Using this correction approach, a resolution of 8.8 ps RMS over a wide temperature range (5 °C to 80 °C) had been achieved in a NUMP-TDC implemented in a Cyclone 10 LP FPGA.
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spelling pubmed-72187342020-05-22 An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction Song, Zhipeng Zhao, Zhixiang Yu, Hongsen Yang, Jingwu Zhang, Xi Sui, Tengjie Xu, Jianfeng Xie, Siwei Huang, Qiu Peng, Qiyu Sensors (Basel) Article This paper presented a non-uniform multiphase (NUMP) time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA) with real-time automatic temperature compensation. NUMP-TDC is a novel, low-cost, high-performance TDC that has achieved an excellent performance in Altera Cyclone V FPGA. The root mean square (RMS) for the intrinsic timing resolution was 2.3 ps. However, the propagation delays in the delay chain of some FPGAs (for example, the Altera Cyclone 10 LP) vary significantly as the temperature changes. Thus, the timing performances of NUMP-TDCs implemented in those FPGAs are significantly impacted by temperature fluctuations. In this study, a simple method was developed to monitor variations in propagation delays using two registers deployed at both ends of the delay chain and compensate for changes in propagation delay using a look-up table (LUT). When the variations exceeded a certain threshold, the LUT for the delay correction was updated, and a bin-by-bin correction was launched. Using this correction approach, a resolution of 8.8 ps RMS over a wide temperature range (5 °C to 80 °C) had been achieved in a NUMP-TDC implemented in a Cyclone 10 LP FPGA. MDPI 2020-04-11 /pmc/articles/PMC7218734/ /pubmed/32290511 http://dx.doi.org/10.3390/s20082172 Text en © 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).
spellingShingle Article
Song, Zhipeng
Zhao, Zhixiang
Yu, Hongsen
Yang, Jingwu
Zhang, Xi
Sui, Tengjie
Xu, Jianfeng
Xie, Siwei
Huang, Qiu
Peng, Qiyu
An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction
title An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction
title_full An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction
title_fullStr An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction
title_full_unstemmed An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction
title_short An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction
title_sort 8.8 ps rms resolution time-to-digital converter implemented in a 60 nm fpga with real-time temperature correction
topic Article
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7218734/
https://www.ncbi.nlm.nih.gov/pubmed/32290511
http://dx.doi.org/10.3390/s20082172
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