Investigating Transactional Memory for High Performance Embedded Systems

We present a Transaction Management Unit (TMU) for Hardware Transactional Memories (HTMs). Our TMU enables three different contention management strategies, which can be applied according to the workload. Additionally, the TMU enables unbounded transactions in terms of size. Our approach tackles two...

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Detalles Bibliográficos
Autores principales: Piatka, Christian, Amslinger, Rico, Haas, Florian, Weis, Sebastian, Altmeyer, Sebastian, Ungerer, Theo
Formato: Online Artículo Texto
Lenguaje:English
Publicado: 2020
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7343417/
http://dx.doi.org/10.1007/978-3-030-52794-5_8

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7343417/
http://dx.doi.org/10.1007/978-3-030-52794-5_8

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