Investigating Transactional Memory for High Performance Embedded Systems

We present a Transaction Management Unit (TMU) for Hardware Transactional Memories (HTMs). Our TMU enables three different contention management strategies, which can be applied according to the workload. Additionally, the TMU enables unbounded transactions in terms of size. Our approach tackles two...

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Detalles Bibliográficos
Autores principales: Piatka, Christian, Amslinger, Rico, Haas, Florian, Weis, Sebastian, Altmeyer, Sebastian, Ungerer, Theo
Formato: Online Artículo Texto
Lenguaje:English
Publicado: 2020
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7343417/
http://dx.doi.org/10.1007/978-3-030-52794-5_8
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author Piatka, Christian
Amslinger, Rico
Haas, Florian
Weis, Sebastian
Altmeyer, Sebastian
Ungerer, Theo
author_facet Piatka, Christian
Amslinger, Rico
Haas, Florian
Weis, Sebastian
Altmeyer, Sebastian
Ungerer, Theo
author_sort Piatka, Christian
collection PubMed
description We present a Transaction Management Unit (TMU) for Hardware Transactional Memories (HTMs). Our TMU enables three different contention management strategies, which can be applied according to the workload. Additionally, the TMU enables unbounded transactions in terms of size. Our approach tackles two challenges of traditional HTMs: (1) potentially high abort rates, (2) missing support for unbounded transactions. By enhancing a simulator with a transactional memory and our TMU, we demonstrate that our TMU achieves speedups of up to 4.2 and reduces abort rates by a factor of up to 11.6 for some of the STAMP benchmarks.
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spelling pubmed-73434172020-07-09 Investigating Transactional Memory for High Performance Embedded Systems Piatka, Christian Amslinger, Rico Haas, Florian Weis, Sebastian Altmeyer, Sebastian Ungerer, Theo Architecture of Computing Systems – ARCS 2020 Article We present a Transaction Management Unit (TMU) for Hardware Transactional Memories (HTMs). Our TMU enables three different contention management strategies, which can be applied according to the workload. Additionally, the TMU enables unbounded transactions in terms of size. Our approach tackles two challenges of traditional HTMs: (1) potentially high abort rates, (2) missing support for unbounded transactions. By enhancing a simulator with a transactional memory and our TMU, we demonstrate that our TMU achieves speedups of up to 4.2 and reduces abort rates by a factor of up to 11.6 for some of the STAMP benchmarks. 2020-06-12 /pmc/articles/PMC7343417/ http://dx.doi.org/10.1007/978-3-030-52794-5_8 Text en © Springer Nature Switzerland AG 2020 This article is made available via the PMC Open Access Subset for unrestricted research re-use and secondary analysis in any form or by any means with acknowledgement of the original source. These permissions are granted for the duration of the World Health Organization (WHO) declaration of COVID-19 as a global pandemic.
spellingShingle Article
Piatka, Christian
Amslinger, Rico
Haas, Florian
Weis, Sebastian
Altmeyer, Sebastian
Ungerer, Theo
Investigating Transactional Memory for High Performance Embedded Systems
title Investigating Transactional Memory for High Performance Embedded Systems
title_full Investigating Transactional Memory for High Performance Embedded Systems
title_fullStr Investigating Transactional Memory for High Performance Embedded Systems
title_full_unstemmed Investigating Transactional Memory for High Performance Embedded Systems
title_short Investigating Transactional Memory for High Performance Embedded Systems
title_sort investigating transactional memory for high performance embedded systems
topic Article
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7343417/
http://dx.doi.org/10.1007/978-3-030-52794-5_8
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