Cargando…

Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits

We introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the location-controlled-grain technique and several innovative low-thermal budget processes, including green nanosecond laser crystallization, far-infrared laser annealing, and hybrid laser-assisted salicidation, that keep...

Descripción completa

Detalles Bibliográficos
Autores principales:	Hsieh, Tung-Ying, Hsieh, Ping-Yi, Yang, Chih-Chao, Shen, Chang-Hong, Shieh, Jia-Min, Yeh, Wen-Kuan, Wu, Meng-Chyi
Formato:	Online Artículo Texto
Lenguaje:	English
Publicado:	MDPI 2020
Materias:	Article
Acceso en línea:	https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7464086/ https://www.ncbi.nlm.nih.gov/pubmed/32751538 http://dx.doi.org/10.3390/mi11080741

Ejemplares similares

Implementation of Gate-All-Around Gate-Engineered Charge Plasma Nanowire FET-Based Common Source Amplifier
por: Singh, Sarabdeep, et al.
Publicado: (2023)

Vertical Gate-All-Around Nanowire GaSb-InAs Core-Shell n-Type Tunnel FETs
por: Vasen, T., et al.
Publicado: (2019)

Evolution of type-II hetero-strain cylindrical-gate-all-around nanowire FET for exploration and analysis of enriched performances
por: Barik, Rasmita, et al.
Publicado: (2023)

Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs
por: Ahn, Tae Jun, et al.
Publicado: (2020)

Fabrication, characterization and simulation of Ω-gate twin poly-Si FinFET nonvolatile memory
por: Yeh, Mu-Shih, et al.
Publicado: (2013)

Effects of Random Nanosized TiN Grain on Characteristic of Gate-All-Around FinFETs with Ferroelectric HZO Layer
por: Li, Yiming, et al.
Publicado: (2022)

A machine learning approach to model the impact of line edge roughness on gate-all-around nanowire FETs while reducing the carbon footprint
por: García-Loureiro, Antonio, et al.
Publicado: (2023)

Nanowire BioFETs: An Overview
por: Meyyappan, M., et al.
Publicado: (2013)

Power Reduction in Punch-Through Current-Based Electro-Thermal Annealing in Gate-All-Around FETs
por: Kim, Min-Kyeong, et al.
Publicado: (2022)

Orientation Effects in Ballistic High-Strained P-type Si Nanowire FETs
por: Zhang, Jia-Hong, et al.
Publicado: (2009)

Design and Optimization of Germanium-Based Gate-Metal-Core Vertical Nanowire Tunnel FET
por: Jang, Won Douk, et al.
Publicado: (2019)

Design of High Performance Si/SiGe Heterojunction Tunneling FETs with a T-Shaped Gate
por: Li, Wei, et al.
Publicado: (2017)

Characterization of a Photodiode Coupled with a Si Nanowire-FET on a Plastic Substrate
por: Kwak, Kiyeol, et al.
Publicado: (2010)

High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits
por: Wu, Tsung-Ta, et al.
Publicado: (2017)

High-speed III-V nanowire photodetector monolithically integrated on Si
por: Mauthe, Svenja, et al.
Publicado: (2020)

Characteristic Fluctuations of Dynamic Power Delay Induced by Random Nanosized Titanium Nitride Grains and the Aspect Ratio Effect of Gate-All-Around Nanowire CMOS Devices and Circuits
por: Li, Yiming, et al.
Publicado: (2019)

Side‐Gated In(2)O(3) Nanowire Ferroelectric FETs for High‐Performance Nonvolatile Memory Applications
por: Su, Meng, et al.
Publicado: (2016)

Back-Gate GaN Nanowire-Based FET Device for Enhancing Gas Selectivity at Room Temperature
por: Khan, Md Ashfaque Hossain, et al.
Publicado: (2021)

Photoconductivity, pH Sensitivity, Noise, and Channel Length Effects in Si Nanowire FET Sensors
por: Gasparyan, Ferdinand, et al.
Publicado: (2018)

Si nanowire Bio-FET for electrical and label-free detection of cancer cell-derived exosomes
por: Zhao, Wenjie, et al.
Publicado: (2022)

Application of Silicon Nanowire Field Effect Transistor (SiNW-FET) Biosensor with High Sensitivity
por: Li, Huiping, et al.
Publicado: (2023)

Novel SiGe/Si Heterojunction Double-Gate Tunneling FETs with a Heterogate Dielectric for High Performance
por: Chen, Qing, et al.
Publicado: (2023)

Analog and RF performance optimization for gate all around tunnel FET using broken-gap material
por: Kumar, Pankaj, et al.
Publicado: (2022)

Diode, transistor & FET circuits manual
por: Marston, R. M.

Special Issue: Nanowire Field-Effect Transistor (FET)
por: Seoane, Natalia, et al.
Publicado: (2020)

Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture
por: Lu, Hongliang, et al.
Publicado: (2019)

Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around
por: Guerfi, Youssouf, et al.
Publicado: (2016)

Nanowire gate all around-TFET-based biosensor by considering ambipolar transport
por: Reddy, N. Nagendra, et al.
Publicado: (2021)

Fabrication of Graphoepitaxial Gate-All-Around Si Circuitry Patterned Nanowire Arrays Using Block Copolymer Assisted Hard Mask Approach
por: Ghoshal, Tandra, et al.
Publicado: (2021)

Improving the High-Temperature Gate Bias Instabilities by a Low Thermal Budget Gate-First Process in p-GaN Gate HEMTs
por: Langpoklakpam, Catherine, et al.
Publicado: (2023)

3D modeling of dual-gate FinFET
por: Mil’shtein, Samson, et al.
Publicado: (2012)

Integrated Logic Circuits Based on Wafer-Scale 2D-MoS(2) FETs Using Buried-Gate Structures
por: Lee, Ju-Ah, et al.
Publicado: (2023)

Novel 14-nm Scallop-Shaped FinFETs (S-FinFETs) on Bulk-Si Substrate
por: Xu, Weijia, et al.
Publicado: (2015)

Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs
por: Gu, Jie, et al.
Publicado: (2021)

High-Performance P- and N-Type SiGe/Si Strained Super-Lattice FinFET and CMOS Inverter: Comparison of Si and SiGe FinFET
por: Yao, Yi-Ju, et al.
Publicado: (2023)

Modeling and Fabrication of Micro FET Pressure Sensor with Circuits
por: Dai, Ching-Liang, et al.
Publicado: (2007)

Nanowire FET Based Neural Element for Robotic Tactile Sensing Skin
por: Taube Navaraj, William, et al.
Publicado: (2017)

Large-Scale Monolithic Fabrication of III–V Vertical Nanowires on a Standard Si(100) Microelectronic Substrate
por: Lecestre, Aurélie, et al.
Publicado: (2022)

Gate-all-around junctionless FET based label-free dielectric/charge modulation detection of SARS-CoV-2 virus
por: Priyadarshani, Kumari Nibha, et al.
Publicado: (2022)

Novel Modeling Approach to Analyze Threshold Voltage Variability in Short Gate-Length (15–22 nm) Nanowire FETs with Various Channel Diameters
por: Lee, Seunghwan, et al.
Publicado: (2022)

Cannot write session to /tmp/vufind_sessions/sess_ih4mmmh5kit88bvr2hq05p1mbe