CMOS-compatible synaptic transistor gated by chitosan electrolyte-Ta(2)O(5) hybrid electric double layer

This study proposes a hybrid electric double layer (EDL) with complementary metal-oxide semiconductor (CMOS) process compatibility by stacking a chitosan electrolyte and a Ta(2)O(5) high-k dielectric thin film. Bio-inspired synaptic transistors with excellent electrical stability were fabricated usi...

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Detalles Bibliográficos
Autores principales: Min, Shin-Yi, Cho, Won-Ju
Formato: Online Artículo Texto
Lenguaje:English
Publicado: Nature Publishing Group UK 2020
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7511302/
https://www.ncbi.nlm.nih.gov/pubmed/32968169
http://dx.doi.org/10.1038/s41598-020-72684-2

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7511302/
https://www.ncbi.nlm.nih.gov/pubmed/32968169
http://dx.doi.org/10.1038/s41598-020-72684-2

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