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Short-Term Memory Dynamics of TiN/Ti/TiO(2)/SiO(x)/Si Resistive Random Access Memory
In this study, we investigated the synaptic functions of TiN/Ti/TiO(2)/SiO(x)/Si resistive random access memory for a neuromorphic computing system that can act as a substitute for the von-Neumann computing architecture. To process the data efficiently, it is necessary to coordinate the information...
Autores principales: | , |
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Formato: | Online Artículo Texto |
Lenguaje: | English |
Publicado: |
MDPI
2020
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Materias: | |
Acceso en línea: | https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7559005/ https://www.ncbi.nlm.nih.gov/pubmed/32932656 http://dx.doi.org/10.3390/nano10091821 |
Sumario: | In this study, we investigated the synaptic functions of TiN/Ti/TiO(2)/SiO(x)/Si resistive random access memory for a neuromorphic computing system that can act as a substitute for the von-Neumann computing architecture. To process the data efficiently, it is necessary to coordinate the information that needs to be processed with short-term memory. In neural networks, short-term memory can play the role of retaining the response on temporary spikes for information filtering. In this study, the proposed complementary metal-oxide-semiconductor (CMOS)-compatible synaptic device mimics the potentiation and depression with varying pulse conditions similar to biological synapses in the nervous system. Short-term memory dynamics are demonstrated through pulse modulation at a set pulse voltage of −3.5 V and pulse width of 10 ms and paired-pulsed facilitation. Moreover, spike-timing-dependent plasticity with the change in synaptic weight is performed by the time difference between the pre- and postsynaptic neurons. The SiO(x) layer as a tunnel barrier on a Si substrate provides highly nonlinear current-voltage (I–V) characteristics in a low-resistance state, which is suitable for high-density synapse arrays. The results herein presented confirm the viability of implementing a CMOS-compatible neuromorphic chip. |
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