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Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM

A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). A poly-Si 1T-DRAM cell operates as a memory by u...

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Autores principales: Yoo, Songyi, Sun, Wookyung, Shin, Hyungsoon
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2020
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7690446/
https://www.ncbi.nlm.nih.gov/pubmed/33105643
http://dx.doi.org/10.3390/mi11110952
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author Yoo, Songyi
Sun, Wookyung
Shin, Hyungsoon
author_facet Yoo, Songyi
Sun, Wookyung
Shin, Hyungsoon
author_sort Yoo, Songyi
collection PubMed
description A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). A poly-Si 1T-DRAM cell operates as a memory by utilizing the charge trapped at the grain boundaries (GBs) of its poly-Si body; vertical GBs are formed randomly during fabrication. This paper describes technology computer aided design (TCAD) device simulations performed to investigate the sensing margin and retention time of poly-Si 1T-DRAM as a function of its lateral GB location. The results show that the memory’s operating mechanism changes with the GB’s lateral location because of a corresponding change in the number of trapped electrons or holes. We determined the optimum lateral GB location for the best memory performance by considering both the sensing margin and retention time. We also performed simulations to analyze the effect of a lateral GB on the operation of a poly-Si 1T-DRAM that has a vertical GB. The memory performance of devices without a lateral GB significantly deteriorates when a vertical GB is located near the source or drain junction, while devices with a lateral GB have little change in memory characteristics with different vertical GB locations. This means that poly-Si 1T-DRAM devices with a lateral GB can operate reliably without any memory performance degradation from randomly determined vertical GB locations.
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spelling pubmed-76904462020-11-27 Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM Yoo, Songyi Sun, Wookyung Shin, Hyungsoon Micromachines (Basel) Article A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). A poly-Si 1T-DRAM cell operates as a memory by utilizing the charge trapped at the grain boundaries (GBs) of its poly-Si body; vertical GBs are formed randomly during fabrication. This paper describes technology computer aided design (TCAD) device simulations performed to investigate the sensing margin and retention time of poly-Si 1T-DRAM as a function of its lateral GB location. The results show that the memory’s operating mechanism changes with the GB’s lateral location because of a corresponding change in the number of trapped electrons or holes. We determined the optimum lateral GB location for the best memory performance by considering both the sensing margin and retention time. We also performed simulations to analyze the effect of a lateral GB on the operation of a poly-Si 1T-DRAM that has a vertical GB. The memory performance of devices without a lateral GB significantly deteriorates when a vertical GB is located near the source or drain junction, while devices with a lateral GB have little change in memory characteristics with different vertical GB locations. This means that poly-Si 1T-DRAM devices with a lateral GB can operate reliably without any memory performance degradation from randomly determined vertical GB locations. MDPI 2020-10-22 /pmc/articles/PMC7690446/ /pubmed/33105643 http://dx.doi.org/10.3390/mi11110952 Text en © 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).
spellingShingle Article
Yoo, Songyi
Sun, Wookyung
Shin, Hyungsoon
Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM
title Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM
title_full Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM
title_fullStr Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM
title_full_unstemmed Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM
title_short Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM
title_sort analysis of a lateral grain boundary for reducing performance variations in poly-si 1t-dram
topic Article
url https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7690446/
https://www.ncbi.nlm.nih.gov/pubmed/33105643
http://dx.doi.org/10.3390/mi11110952
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