Power-Oriented Monitoring of Clock Signals in FPGA Systems for Critical Application

This paper presents a power-oriented monitoring of clock signals that is designed to avoid synchronization failure in computer systems such as FPGAs. The proposed design reduces power consumption and increases the power-oriented checkability in FPGA systems. These advantages are due to improvements...

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Detalles Bibliográficos
Autores principales: Drozd, Oleksandr, Nowakowski, Grzegorz, Sachenko, Anatoliy, Antoniuk, Viktor, Kochan, Volodymyr, Drozd, Myroslav
Formato: Online Artículo Texto
Lenguaje:English
Publicado: MDPI 2021
Materias:
Article
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7865678/
https://www.ncbi.nlm.nih.gov/pubmed/33503980
http://dx.doi.org/10.3390/s21030792

Internet

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7865678/
https://www.ncbi.nlm.nih.gov/pubmed/33503980
http://dx.doi.org/10.3390/s21030792

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