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Impact of device scaling on the electrical properties of MoS(2) field-effect transistors

Two-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fab...

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Detalles Bibliográficos
Autores principales: Arutchelvan, Goutham, Smets, Quentin, Verreck, Devin, Ahmed, Zubair, Gaur, Abhinav, Sutar, Surajit, Jussot, Julien, Groven, Benjamin, Heyns, Marc, Lin, Dennis, Asselberghs, Inge, Radu, Iuliana
Formato: Online Artículo Texto
Lenguaje:English
Publicado: Nature Publishing Group UK 2021
Materias:
Acceso en línea:https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7987965/
https://www.ncbi.nlm.nih.gov/pubmed/33758215
http://dx.doi.org/10.1038/s41598-021-85968-y
Descripción
Sumario:Two-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS(2) material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS(2) transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices.